1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically, to a layout technique of memory cells and peripheral I/Os in a semiconductor memory device.
2. Description of Related Art
Although memory cells have been reduced in size in accordance with miniaturization of processes in semiconductor manufacturing, reduction in size of pads for packaging or the like is not sufficient. Further, increase in the number of pads has been significant in accordance with the increase of the number of product functions, and it is desired to mount as many pads as possible without increasing the size of the chip.
FIG. 4 shows a pattern layout of a semiconductor memory chip assembled in a flip chip package disclosed in Japanese Patent No. 3990125 (Yabe et al.) (patent document 1). In this memory chip, a memory cell array is divided into a plurality of subarrays arranged in matrix form. In this example, the memory cell array is divided into subarrays SA1,1 to SA16,16 of a matrix with 16 rows and 16 columns. Thus, the p-th subarray column (p is an integer smaller than 17) includes sixteen subarrays SAp,1 to SAp,16.
A first peripheral circuit area 11 is formed in a middle section of a subarray matrix, which extends in the column direction, and a second peripheral circuit area 12 is formed in a middle section of the subarray matrix, which extends in the row direction. The first peripheral circuit area 11 supplies a subarray control signal to each of sixteen subarrays SAp,1 to SAp,16 included in the p-th subarray column.
In this example, the first peripheral circuit area 11 is interposed between the eighth and ninth rows of the subarray matrix and includes sense amplifiers. The second peripheral circuit area 12 is interposed between the eighth and ninth columns of the subarray matrix and includes main row decoders. External connection pads are arranged in a middle section of the subarray matrix, which extends in the column direction. In this example, a first pad area 21 is formed between the fourth and fifth rows of the subarray matrix and a second pad area 22 is formed between the twelfth and thirteenth rows thereof.
Paying attention to the first subarray column as a representative example, the first peripheral circuit area 11 supplies subarray control signals from control signal drivers DRV1 to DRV16 to sixteen subarrays SA1,1 to SA1,16 via subarray control signal lines S1,1 to S1,16, respectively.
Subarray control signal lines S1,1 to S1,4 extend to their respective subarrays (SA1,1 to SA1,4), which are located away from the first peripheral circuit area 11, from the first periphery circuit area 11 through the first pad area 21. Subarray control signal lines S1,13 to S1,16 extend to their respective subarrays (SA1,13 to SA1,16), which are located away from the first peripheral circuit area 11, from the first periphery circuit area 11 through the second pad area 22.
FIG. 5 is an enlarged view showing an example of the pattern layout in a neighborhood of the first pad area 21 shown in FIG. 4. For the sake of simplification of layout design, a plurality of subarray control signal lines Sp,1 to Sp,16 are arranged on the p-th subarray column at the same pitches as those of the subarray columns and thus designed hierarchically.
The first pad area 21 includes a plurality of pads Pd and these pads are arranged in the row direction at the same pitches as those of the subarray columns. In the first embodiment, the pads Pd are located on their respective boundaries of the subarray columns, as indicated by the dotted lines in FIG. 4. The second pad area 22 includes a plurality of pads Pd and these pads Pd are arranged in the row direction at the same pitches as those of the subarray columns and located on their respective boundaries of the subarray columns, as indicated by the dotted lines in FIG. 4.
At least some (Sp,1 to Sp,4 and Sp,13 to Sp,16) of the subarray control signal lines Sp,1 to Sp,16, which are connected between the first peripheral circuit area 11 and the subarrays of the subarray columns, are formed linearly such that they can pass between the pads Pd of the first pad area 21 and between the pads Pd of the second pad area 22.
In this example, all the subarray control signal lines Sp,1 to Sp,16 are formed to have the same length as that of a signal line connecting the subarrays SAp,1 and SAp,16 that are farthest from the first peripheral circuit area 11. Furthermore, all the subarray control signal lines Sp,1 to Sp,16 are formed linearly such that they can pass between the pads Pd. The memory chip disclosed in Yabe et al. can be summarized as follows. The memory cell array is divided into subarrays SA1,1 to SA16,16 arranged in matrix form. The peripheral circuit areas 11 and 12 and pad areas 21 and 22 are formed in the middle sections of the subarray matrix. In the pad areas 21 and 22, the plurality of pads Pd are arranged at the same pitches as those of the subarrays, and the subarray control signal lines Sp,1 to Sp,16, which connect the peripheral circuit area 11 and each of the subarrays, are linearly formed such that they can pass between the pads Pd.
The same pattern can thus be designed for each subarray column in laying out the subarray control signal lines Sp,1 to Sp,16. As such, the subarray control signal lines Sp,1 to Sp,16 are not turned so as to detour around the pads of the pad areas 21 and 22 formed halfway through the subarray columns, they can be prevented from increasing in parasitic capacitance and parasitic resistance of the signal lines. Thus, the variations of delay time of subarray control signals supplied to the subarrays can be suppressed, with the result that a high-speed memory chip can be designed.
In order to achieve a high-speed memory such as an SRAM, an SRAM chip capable of a high-speed operation as this example is formed. Then, the SRAM chip is bonded to a chip assembly substrate (not shown) by flip chip bonding and assembled in a package (usually resin-molded). The subarray control signal lines Sp,1 to Sp,16 are formed to have the same length as that of a signal line connecting the subarrays that are farthest from the first peripheral circuit area 11, thereby keeping the parasitic capacitances and parasitic resistances of the respective signal lines constant. Meanwhile, Japanese Unexamined Patent Application Publication No. 8-116036 (patent document 2) discloses a technique of arranging pads on both sides of a memory array.